Huỳnh Văn Nhất

Huỳnh Văn Nhất

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Ông: Huỳnh Văn Nhất

Thạc sĩ hệ thống thông tin đại học Osaka
Kỹ sư tại tập đoàn Sony – Tokyo Nhật Bản
Đã nộp 4 bằng sáng chế


To use current knowledge, experience of image processing, hardware and system development to make algorithms, solutions for ADAS/AD involving image and sensor technology.


  • Currently research and Developing the advanced sensing technology aiming for camera system of smart-phone and IoT
  • Talented professional with 10 years in hardware development (RFQ analysis, specification, design, test, customer support) and high skills of Verilog, SystemC, Low power design, FPGA, Palladium
  • Talented professional with 10 years in developing image signal processing algorithm such as resizing, FIR/IIR filtering, noise reduction, color conversion, color balancing, I/P conversion, Object tracking filter, Haar-like cognitive filter
  • Excellent experience with 10 years in developing software in C/C++ with Microsoft Visual Studio, gcc, g++
  • High experience with 4 years in designing and evaluating function & performance of bus/QoS system, camera system (CSI2), display system (DRGB, LVDS, HDMI, MIPI CSI2/DSI2)
  • Industry experience in developing image stitching solution (both sw and hw) using multiple cameras for free-view point surround view, E-mirror targeting for ADAS
  • Industry experience in ASIL-B safety function design
  • Excellent experience with 6 years in project leader, assistant of managing technology, schedule, human & machine resources, training new engineer
  • Excellent experience with 6 years in making design requirement to subsidiary development team
  • High confidence in studying and adopting inexperienced technology, method, tools
  • High challenge spirit in overcoming difficult problems and making new value
  • Filed 4 patents about “Avoidance of memory bank conflict ion”, “Advertise synergy in autonomous car service”, “High loss-less compression”, “Applying block-chain in tolerant ADAS processing”

Career History


Sony Corp., Tokyo, Japan April 2019 – Present

Career Division: Image Sensor


Renesas Electronic, Corp., Tokyo, Japan   April 2017 – March 2019

Career Division: Hardware Designer


Project leader

  • Study/research the solutions of free viewpoint surround view for ADAS and electronic mirror
  • Analyze HW development requirements (image processing, display processing, safety function ASIL-B, bus performance) and drop into functional specifications
  • Design the bus sub-system satisfies 1200Mpixs/sec
  • Design the display system of standard DSI2 and camera input system CSI2
  • Design safety function to achieve criteria of ASIL-B
  • Develop and evaluate the algorithm of image processing (color adjustment, noise reduction) with VS
  • Make requirement spec of detail design to subsidiary’s development team
  • Project management (schedule setting, role assignment, progress management, quality control, etc)
  • Evaluate process performance, bus performance and image quality
  • QA support to customers and SW designers



  • I lead my team of 9 members completed all the targets through 9 months before the schedule
  • By cooperating with marketing team, SW team in investigation of surround-view, e-mirror solution I could decide the HW specification at early stage and therefore I could get margin schedule for HW development.
  • In order to clear up the technical issues of the free viewpoint surround view solution, I studied and understood fundamentally the principle of photo-sensor and other inexperienced technologies such as correlation between color and light, and figured out and resolved the dispersion problem between cameras
  • I realized 90% exceeding ASIL-B's LFM target failure detection rate.
  • In order to overcome the adverse circumstances in which the replacement of project members frequently occurred, I adjusted the development strategy flexibly and became the preliminary completion team in LSI development as well as the realization of 0 defects.


Renesas Electronic, Corp., Tokyo, Japan                                       Apr 2007 – April 2017

Career Division: Hardware Designer


Project sub-leader

  • Development of image processing / display system of R-Car Gen 3 series
  • Development of AXI compliant image processing IP of R-Car Gen 2 series
  • Frame rate conversion IP development of R-Car Gen 1 series

Project member

  • Image scaling IP, image blending IP development for SH-Mobile G3 series
  • Variable Flow Multi-function Image Processing IP Development for SH-Mobile G4 Series
  • Low power image processing / display IP development for R-Mobile series and R-Car Gen 1 series


  • Solved memory bank conflict problem with multiple IP simultaneous access. Filed one patent on Nov. 2017.
  • Developed the bus lossless and lossy compression method achieved 50% bandwidth reduced in R-Car Gen3.
  • In the short-term development, I adopted the new design method SystemC and shorten the half of schedule
  • I focused on backward compatibility of SW interface so as not to cause malfunction of existing SW
  • I designed the bus response buffer basing on a model and configurable for any subsequent products.
  • To prevent schedule bottleneck due to workload superb load and bias of assignment, I flattened the team members so that communication is smooth and tasks are easily shared.
  • For the project which has strict schedule I make the requirement specification in detail to subsidiary team to prevent risky defects. However, if the schedule has enough margin I make requirement specifications outline in order to train the development ability leading to outsourced quality.



University of Osaka                                                                                 Apr 2001 – Mar 2004

Bachelor of electronic information and energy

University of Osaka                                                                                 Apr 2005 – Mar 2007

Master degree of Information System


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